Sr. Component Design Engineer – 556640 |
| Aug. 21, 2008 - Aug. 15, 2009 |
| Location: | Phoenix, AZ |
| Employment Type: | Full Time |
| Employer: | Intel |
| Description: | The System-On-a-Chip Enabling Group (SEG) provides IP building blocks that other teams within Intel integrate into their products. For example, SEG IP blocks were used in the Canmore chip that Paul demonstrated in his keynote address at the Consumer Electronics Show this year. Within SEG, the Hard-IP Logic team develops the digital logic blocks that work in concert with analog blocks within our high speed serial PHY's. such as the PHY's for PCI-Express, Serial ATA, and USB. Examples of the logic blocks include digital filters, PHY block sequencing control, data alignment, compensation control, and others. In this position, you will be developing digital logic, validate and synthesize logic, and developing simulation models for analog circuit blocks. We are looking for logic validation engineers who have experience with creating self-checking test benches, writing and executing test plans, and debugging tests and RTL designs |
| Qualifications: | You will possess a Bachelor or a Master of Science degree in Electrical Engineering or equivalent degree and more than three years of applicable experience. In addition to validation skills, candidates with secondary skills, such as RTL design or synthesis and static timing analysis is preferred. You should be knowledgeable with Verilog* and System Verilog*. General knowledge of logic architectures related to PHY's (clock recovery architectures, clock crossing FIFOs, data scrambling/descrambling, data encoding and/or decoding) would be an added advantage. |
|
|
This job is no longer active. Please click here to see current job listings.
|
|
|
